----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:29:42 11/16/2010 
-- Design Name: 
-- Module Name:    One_hot_count4 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use WORK.CONSTANTS.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity One_hot_count4 is
    Port ( reset : in  STD_LOGIC;
           advance : in  STD_LOGIC;
			  clk : in STD_LOGIC;
           count_out : out  STD_LOGIC_VECTOR (ADDR_SIZE_CONFBUFFER-1 downto 0) );
end One_hot_count4;

architecture Behavioral of One_hot_count4 is
	signal count : STD_LOGIC_VECTOR (ADDR_SIZE_CONFBUFFER-1 downto 0) := "0001";
	begin     
	count_out <= count;
	one_hot_count : process (clk, advance, reset)
	
	begin
		if reset = '1' then
			count(0) <= '1';
			count(ADDR_SIZE_CONFBUFFER-1 downto 1) <= (others => '0');
		elsif clk'event and clk = '0' then
			if advance = '1' then
				count <= count(ADDR_SIZE_CONFBUFFER-2 downto 0) & count(ADDR_SIZE_CONFBUFFER-1);
			else		
			end if;
		end if;	
	end process;

end Behavioral;
